Synthesizing Hardware from Dataflow Programs

Synthesizing Hardware from Dataflow Programs

The MPEG Reconfigurable Video Coding working group is developing a new library-based process for building the reference codecs of future MPEG standards, which is based on dataflow and uses an actor language called Cal. The paper presents a code generator producing RTL targeting FPGAs for Cal, outlines its structure, and demonstrates its performance on an MPEG-4 Simple Profile decoder. The resul...

Rapid Prototyping of Dataflow Programs on Hardware/Software Architectures

In this paper, the problem of automatically mapping large-grain data ow programs onto heterogeneous hardware/software architectures is treated. Starting with a given hardware/software partition, interfaces are inserted into the speci cation to account for communication, in particular across hardware/software boundaries. Depending on the target architecture, the interfaces are re ned according t...

Combining P2 and RDL to build Dataflow Hardware Programs

Synthesizing Hardware from Object-Oriented Descriptions1

Hardware synthesis from programming languages, including object-oriented ones such as C++ and Java, has recently attracted a lot of interest from researchers and users. Increasingly, the object-oriented aspect is being stressed. In this paper, several approaches to describing hardware by means of object-orientation are investigated with respect to their support for synthesis. We have formulated...

Synthesizing FPGA Circuits from Parallel Programs

From silicon to science : the long road to production reconfigurable supercomputing p. 2 The von Neumann syndrome and the CS education dilemma p. 3 Optimal unroll factor for reconfigurable architectures p. 4 Programming reconfigurable decoupled application control accelerator for mobile systems p. 15 DNA physical mapping on a reconfigurable platform p. 27 Hardware BLAST algorithms with multi-se...